Thursday, March 29, 2012

30th March 2012 Class

Need to postpone today's class as the department is having a whole day workshop. See you all after mid-term break. Be prepared for midterm examination immediately after holiday.

Emran Mohd Tamil

Thursday, March 22, 2012

Class on 23th March

Class on 23th March will start at 2:30PM (half an hour faster than schedule) after friday prayer. Thank you.

Emran Mohd Tamil.

Thursday, March 15, 2012

16th March 2012 Class

Class on 16th March will start at 2:30PM (half an hour faster than schedule) after friday prayer. Thank you. Emran.

Thursday, December 22, 2011

Midterm result & re-sit

You can view your midterm result at the following link (Please take not these mark is not moderated yet, so there might be changes after moderation)

Those with mark less than 10 can optionally re-sit the midterm tomorrow (23rd Dec) at 3PM at one of the tutorial room (any room that is available). The new mark for those who re-sit would be the average from the first one and the re-sit version. Please note that questions are relatively much tougher than the previous set. Topic is until combinational circuit.

Congratulation to those who manage to score full mark.

Wednesday, December 21, 2011

Assignment

Your assignment number is the last number in your matrix number. So if your matrix number is WET100112 then your assignment number is 2.

Do and simulate in multisim the following converter. Submit the completed circuit file and report in doc/pdf format (brief report like your sequential report) to drziner@gmail.com (please put your matrix number as the subject in your email)

Assignment
0. Input: 4 bit signed magnitude Output: 5 bit 2nd complement
1. Input: 4 bit signed magnitude Output: 5 bit 1st complement
2. Input: 4 bit BCD Output: 4 bit Gray code
3. Input: 4 bit Excess-3 Output: 4 bit Binary
4. Input: 4 bit 1st complement Output: 4 bit sign magnitude
5. Input: 4 bit 2nd complement Output: 4 bit sign magnitude
6. Input: 4 bit binary Output: parity even
7. Input: 4 bit binary Output: parity odd
8. 2 bit input half adder (input A,B output C,S)
9. 3 bit input full adder (input A,B,Cin output C,S)

Last date of submission: 30th Dec 2011

Tuesday, November 15, 2011

Mid term examination will be held on 17 Nov 2011 at DK 2, FSKTM from 1-2pm

Study all topic until combinational circuit. Thank you

Tuesday, October 4, 2011

Tutorial 6/10/2011

For the tutorial class tomorrow (6/10/2011), please prepare for the following questions

1. Convert +10 (decimal) to
a) binary code (4 bits)
b) gray code (4 bits)
c) excess 3 code (4 bits)
d) BCD code
e) BCD 84-2-1

2. Convert -10 (decimal) to
a) sign-magnitude (5 bits)
b) 1st complement (5 bits)
c) 2nd complement (5 bits)

3. Generate the ODD parity bit for the following data
a)1101
b)0000
c)1111

4. Generate the hamming code for the following data
a)1101
b)1101001

5. Try to change one bit from the hamming code produced from question 4 and then run the hamming code checking to determine which bit that has been changed.

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