Thursday, December 22, 2011

Midterm result & re-sit

You can view your midterm result at the following link (Please take not these mark is not moderated yet, so there might be changes after moderation)

Those with mark less than 10 can optionally re-sit the midterm tomorrow (23rd Dec) at 3PM at one of the tutorial room (any room that is available). The new mark for those who re-sit would be the average from the first one and the re-sit version. Please note that questions are relatively much tougher than the previous set. Topic is until combinational circuit.

Congratulation to those who manage to score full mark.

Wednesday, December 21, 2011

Assignment

Your assignment number is the last number in your matrix number. So if your matrix number is WET100112 then your assignment number is 2.

Do and simulate in multisim the following converter. Submit the completed circuit file and report in doc/pdf format (brief report like your sequential report) to drziner@gmail.com (please put your matrix number as the subject in your email)

Assignment
0. Input: 4 bit signed magnitude Output: 5 bit 2nd complement
1. Input: 4 bit signed magnitude Output: 5 bit 1st complement
2. Input: 4 bit BCD Output: 4 bit Gray code
3. Input: 4 bit Excess-3 Output: 4 bit Binary
4. Input: 4 bit 1st complement Output: 4 bit sign magnitude
5. Input: 4 bit 2nd complement Output: 4 bit sign magnitude
6. Input: 4 bit binary Output: parity even
7. Input: 4 bit binary Output: parity odd
8. 2 bit input half adder (input A,B output C,S)
9. 3 bit input full adder (input A,B,Cin output C,S)

Last date of submission: 30th Dec 2011

Tuesday, November 15, 2011

Mid term examination will be held on 17 Nov 2011 at DK 2, FSKTM from 1-2pm

Study all topic until combinational circuit. Thank you

Tuesday, October 4, 2011

Tutorial 6/10/2011

For the tutorial class tomorrow (6/10/2011), please prepare for the following questions

1. Convert +10 (decimal) to
a) binary code (4 bits)
b) gray code (4 bits)
c) excess 3 code (4 bits)
d) BCD code
e) BCD 84-2-1

2. Convert -10 (decimal) to
a) sign-magnitude (5 bits)
b) 1st complement (5 bits)
c) 2nd complement (5 bits)

3. Generate the ODD parity bit for the following data
a)1101
b)0000
c)1111

4. Generate the hamming code for the following data
a)1101
b)1101001

5. Try to change one bit from the hamming code produced from question 4 and then run the hamming code checking to determine which bit that has been changed.

Wednesday, September 28, 2011

Tutorial Class 12-1,1-2

Please come to BT2 & BT1 to check your tutorial grouping at 12:00 PM. thank you.

Emran Mohd Tamil

Monday, September 12, 2011

Notice for Group Assignment/Demonstration

UPDATE: During the lecture today we will discuss how to demonstrate this assignment.

Create a group of 10 student (max 10, min 8)

Download Multi Student Edition from here https://lumen.ni.com/nicif/us/evalmultisim/content.xhtml or download directly from here http://ftp.ni.com/evaluation/labview/ekit/other/downloader/NI_Circuit_Design_Suite_11_0_2_Education_downloader.exe

Familiarized & learn how to use the software. You should be able to run sample circuit provided within the software sample folder. Choose one sample circuit, modify it & simulate it. Demonstrate next Thursday (the time & place for demonstration will be updated here, most probabily between 1-2 before the class).

Lecture slide download link partially fixed, you can now download the first few slides (until Boolean Algebra) . The other link will be updated later.

Thursday, October 7, 2010

Group Project

You can view the group list & viva schedule from here. The grouping is FINAL. No addition/changes/modification is allowed.

Design a counter circuit from your own matrix number
1. Omit the 2nd/3rd/4th duplicate in your matrix number. For example if your matrix is 090093 it will be 093
2. The number would be your state in the counter design. Do a backward counter from the number. For example if the number is 093 then the counter would be 0 --> 3 --> 9 --> 0
3. Choose any type of FF that  you want to use in your counter (ie JK FF, SR FF, T FF, D FFF). Complete the corresponding next state table and sequential circuit
4. Draw the circuit in MultiSim simulator (you can download the student evaluation version from here) . During the viva you need to demonstrate the circuit is functioning as it should be (use the 7 bit led segment to show the counter)

Assessment & Submission
The marks for this group project is 15%.  Mark would be derived from the percentage of successful simulation. For example if 8 out of 10 circuit successfully simulated then the marks would be 16.

You also need to submit the documentation by group in CD format (1 CD pergroup). The documentation will be another 5% (to be marked individually). Documentation should consist
-documentation in doc/docx/pdf format
-circuit softcopy
Arrange the documentation in individual folder using the matrix number as the folder title (eg WEK100001,WET0900706)

Tips
tips: Your senior has done a similar project to this one. Request assistance from them especially in how to use the simulation software. Electrical student should also has some experience using similar software.

(The group mark is reduced from 20% to 15% to accomodate assessment from quizes done during your tutorial session)

Warning
Any case of possible plagiarism/copying will be dealt severely. Not only BOTH OF YOU will get zero for your assessment , the department will report the case to the university discipline board which upon conviction might expel/suspend you from the course.

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